With the recent tendencies for electronic equipment to have smaller size and weight, semiconductor chip packages for mounting have been reduced in dimensions. In this line, so-called chip size packages (also called chip scale packages) have been developed as means for providing minimally packaged chips which are about the size of bare chips.
As shown in FIG. 14, a chip size package is mounted on an external wiring board 2 with an interposer 3 interposed therebetween to establish electrical connections between the electrodes (not shown) of the chip 1 and the electrodes 12 of the external printed wiring board 2.
The interposer 3 has an outer insulator layer 6, a conductor layer 4 formed on the outer insulator layer 6 in a prescribed circuit pattern, and an inner insulator layer 5 formed thereon. The inner insulator layer 5 have inner via-holes 7 mated with the electrodes of the chip 1, and inner electrodes 8 are formed in the inner via-holes 7. The outer insulator layer 6 has outer via-holes 9 mated with the electrodes 12 of the external circuit board 2, in which outer electrodes 10 are formed. Solder balls 13 are connected to the outer electrodes 10.
The inner insulator layer 5 of the interposer 3 is joined to the back face of the semiconductor chip 1 to connect the inner electrodes 8 and the electrodes of the chip 1. In surface mounting, the outer electrodes 10 of the package are connected to the electrodes 12 of the external circuit board 2 via the solder balls 13, whereby electric connections between the electrodes of the chip 1 and those of the external printed wiring board 2 are established through the inner electrodes 8, the conductor layer 4, the outer electrodes 10, and the solder balls 13 of the interposer 3. The semiconductor chip 1 has been sealed with a sealant 11.
In producing the interposer 3, where the inner electrodes 8 and the outer electrodes 10 are formed by electroplating, it is necessary to form plating leads in the conductor layer 4. However, lead formation often restricts the arrangement or the interval of the electrodes, failing to form electrodes at a fine pitch and a high density. As a result, difficulties are often met with in efficiently reducing the interposer 3 in size. Further, if the plating lead remains in the resulting interposer 3, it tends to induce a crosstalk which causes a noise.